Digital antenna scan pattern generator

ABSTRACT

A device for generating simulated scan patterns of conventional search radar antennas comprising an electronic pulse generator, a delay pulse width control unit, decoding means to apply a pulse sequentially to one in a series of individually adjustable load potentiometers, and an OR gate connected to the wiper arms of the potentiometers, thus providing as an output a sequential train of pulses whose amplitude can be set to reflect a desired antenna pattern.

Elite States atet 11113 63433 I 72] Inventor Theodore W. Synowka [56] References Cited 1919 Norwich Road, Glen Burnie, Md. UNITED STATES PATENTS 21061 3,184,734 5/1965 Uren etal. 340/347 g i' 3 1969 3,374,481 3/1968 Lupinetti 343/177 6 3,216,001 11/1965 l-linrichs 340 347 AD [45] Patented Jan. 11, 1972 Continuation-impart of application Ser. No. Primary Examiner-Daryl W. Cook 582,202, Sept. 22, 1966, now abandoned, Assistant Examiner-Leo H. Boudreau This application Aug, 27, 1969, S No, Attorneys-William G. Gapcynski and Lawrence A, 853,352 Neureither [54] DIGITAL ANTENNA SCAN PATTERN ABSTRACT: A device for generating simulated scan patterns GENERATOR of conventional search radar antennas comprising an electronic pulse generator, a delay pulse width control unit,

5 Claims, 4 Drawing Figs.

decoding means to apply a pulse sequentially to one in a series [52] US. Cl 340/33; lD7A7, of individually adjusmble load Potentiometers and an OR gate 51 I t 03k 13 4 connected to the wiper arms of the potentiometers, thus 1 n providing as an output a sequential train of pulses whose am- [50] Field of Search 340/347, pmude can be Set to reflect adasired antenna pattern.

OPERATE Ll L2 5 GALIBRATE I s H up v a 025 I on? can r1 w: r: in F! re :1 Fl we no in n: Ila IJFIH no r11 FII In F20 F21 F22 F23 P21 F2: :26 I21 ran F29 no r31 r32 EPATENTED Jun 1 1912 3.6341886 SHEET 1 OF 2 IIIIIIlIIII.llllllllIlIllll lll'lllllIl-IIII'IIIIIIIIIIIIII'. I

FATENTED JAN] 1 $72 SHEET 2 BF 2 ANTENNA GAIN PATTERN DEGREES FROM ANTENNA CENTRAL AXIS SIMULATED TARGET RETURN ECHO PULSES I 4 B D D wm sm PLEMDD FlG.4

INVET-JTOR THEODORE W. SYNOWKA ATTORNEY DIGITAL ANTENNA SCAN PATTERN GENERATOR CROSS REFERENCE TO RELATED APPLICATIONS This application is a continuation-in-part of application Ser. No. 582,202, filed Sept. 22, 1966, now abandoned.

BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to a digital electronic device which generates simulated scan patterns of a conventional radar antenna.

2. Description of the Prior Art In applications requiring simulation of the radar target echo pulses which appear at the video output of. a conventional search radar, characteristics such as scintillation, antenna gain pattern, thermal noise, and target distance must be accounted for in the simulator system. This invention is particularly concerned with providing means for simulating the effect of the antenna gain pattern on the target echo pulses.

Radar systems normally employ directive antennas for transmission and reception, and the gain of theseantennas is a function of the angular distance of the target from the axis of maximum sensitivity of the antenna. In practice, the target will be on the axis of maximum antenna gain for only a short amplitude of the returned pulses will be modulated by the shape of the antenna gain pattern.

The problem of generating a series of pulses whose amplitude varies according to a particular antenna pattern has been solved by prior art devices utilizing electromechanical techniques. Although a fairly satisfactory pattern can be generated by electromechanical means, significant drawbacks are inherent in these methods. Since most of the prior art devices include a motor driving a shaped potentiometer, these devices are expensive, are subject to wear on the movable parts, and are able to generate only one pattern shape.

SUMMARY OF THE INVENTION The invention simulates the antenna pattern modulation of target echo pulses by digital electronic means. A source of pulses is encoded by a counter unit, and the pulsesare then decoded by a plurality of NAND gates so that a plurality of circuits comprising a voltage source and a variable potentiometer are individually and sequentially enabled. The voltage outputs from the potentiometer wiper arms are connected to an OR gate so that the system output is a'train of pulses whose amplitudes may be individually set to simulate a desired antenna pattern.

Accordingly, it is an object of this invention to provide a re liable and inexpensive digital electronic system to simulate an antenna scan pattern.

It is a further object of this invention to provide an antenna scan pattern generator with capability of generating a plurality of different scan patterns.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a wiring diagram of the invention.

F IG. 2 is a graph of the gain curve of a radar antenna.

FIG. 3 is the graph of the output voltage of the invention corresponding to the simulated antenna pattern of the antenna of FIG. 2.

FIG. 4 is a functional diagram of one of the bistable units.

DESCRIPTION OF THE PREFERRED EMBODIMENT Referring to FIG. I, the invention comprises a pulse generator l, a delay/pulse width control unit 2, a counter 3, a decoder unit 4, a plurality of potentiometer load resistors 5, and an output OR-gate 6. The pulse generator 1 generates a continuous train of pulses at a repetition rate which can be adjusted to meet various application requirements, typically between 250 and 1,500 pulses per second. The output of the pulse generator I is connected to the delay/pulse width con period of time, and as the antenna scans past the target, the

trol unit 2 and also to the counter 3 through NAND-gates 7 and 8. The counter 3 is comprised of six bistable multivibrator units, Al, A2, A3, A4, A5 and A6, serially connected so that the output of one bistable unit provides the input to the next bistable unit, and the counter will change states with each application of an input pulse, Connected in this manner the counter will assume 2 or 64 unique states in response to pulses from the pulse generator, and after the 64th pulse it will recycle and assume its original state. Each bistable unit is provided with two outputs, one of which will be a logical l and the other will be a logical 0 at a given instant.

Referring to FIG. 4, a bistable unit functional diagram is shown. When used as a binary counter element, the clocked set S0 is connected to Q, and the clocked reset RO is connected to 6. Thus, on each negative going clock pulse applied at C, the output of the bistable unit will change state. The 0 output will be a l (voltage output) in the set state and 0 (ground) in the reset state. The 6 output will always be opposite to the Q output. A ground applied to terminal S will set the bistable unit, and the Q output will be a l The application of a ground to the R terminal will reset the bistable unit, and the 0 output will be a 0.

The pulses from the pulse generator 1 also are directed into the delay/pulse width control unit 2 and a fixed time delay, to simulate the echo return time, is introduced. Means are also included to vary the width of the pulse. These functions may be accomplished by conventional circuits; for example, through the use of a monostable multivibrator and a delay line.

The output of the delay/pulse width control unit 2 and the outputs from the bistable units A1 through A6 are interconnected to the decoder unit 4 according to conventional logical theory so that one output pulse is produced at one decoder output line for a period of time equal to the length of the pulse from the delay/pulse width control unit 2. To illustrate the operation of the decoder unit the process of producing one output pulse will be discussed.

The decoder unit is comprised of a plurality of NAND-gates which can be described by the truth table shown below in which a l condition represents voltage presence and a 0" represents the absence of a voltage:

The 0" condition at the output, which is produced only by a l at each input, will be referred to as the enabled state in describing the operation of the gate, and the tenn disabled will be used to refer to the presence of a l at the output.

An example of the decoding followsz assume the counter was originally set at zero and has received three pulses. This state requires a l state at A1 and A2 and 0" state at A3, A4, and A5. Consequently, a l condition will also exist at 3 3 A2, A5 and a 0 condition will exist at AT and A2. Examination of FIG. 1 will show that only gate B 5 of the B seri e s of gates is enabled at this time as its inputs A3, A4, and A5 each are in the l state. The enabled output of gate B5 is inverted by gate C5 so that a l is present at point P5. Examination of gates B1, B2, B3, and B4 reveals that the inputs to these gates consist of a combination of the delayed pulse am the pulse generator 1 and any two of Al, A2, AT, and 2. Since the pulse from the pulse generator will be present r a preselected period in each count, then enabling of one of e four gates depends on presence of the proper combination will be described. For simplicity of illustration the scan rate will be chosen so that echo pulses are returned for each 20 differential from the zero axis of the antenna. From F IG. 2 the following relative values of the echo pulse as a function of the Al A2, 1, and .6. There are four possible combinations angular distance of the target from the zero axis of the antenna Al, A2, A l, and A 2, and each is represented by the input can be derived:

inditions at one of gates B1, B2, B3, or B4. Thus on each aunt one of the gates B1, B2, B3, or B4 will be enabled for a :riod of m w to the pulse width selepted by the Distance from the Relative Strength of Pulse :lay/pulse width unit 2, and the enablement will occur at a Antenna Axis the e pulse Number ne after the generation of the input pulse from the pulse M I :nerator l which is equal to the delay introduced by the :28: :1: g:-

:lay/pulse width control unit 2. Since Al and A2 are each in e 1" state when the count of three is in the counter unit, -zo 2.s db. l3

vte B4 will be enabled when the delayed pulse from the 0 0 :lay/pulse width control unit is applied. The enabled output :38: 15: g:

)m B4 is inverted by C4 so that a l is present at P4. The 5 25 rmbination of l on P4 and P5 will enable only gate D3 in +80 rs db. 28

e D series of gates. When gate D3 is enabled, the circuit )m the positive power supply through R33 and potentiomer R3 and diode F3 to ground is completed. The voltage at e output 9 at the junction of R33 and diodes F1 through F32 To program the scan Pattern generator for this Particular ll b a f i f h value set on t ti t R3, d it antenna function, switch S7 is placed in the calibrate position,

1] b present at th output 9 f a i d f tim equal t th and switch S8 is momentarily closed to reset the counter to the llse width selected by the delay/pulse width ontrol unit 2. zero state. Then switch S1 is closed to place a binary count of Thus, as each driving gate is enabled, the voltage at the out- 100,000 in the counter. This count means that Al is in the l it 9 will be a function of the setting of the potentiometer as- State n A2, A and A6 are n the statfl Thus,

ciated with each gate; by setting the potentiometers apgate B5 will be enabled, and gate B2 will be enabled by the opriately, a wide variety of output functions can be simu- 30 delayed pulse from the delay/pulse width control unit 2. The

;ed. in the present embodiment one driving gate is enabled output from these two gates will be inverted by gates C5 and r each of the first 32 counts of the counter; on the 33rd pulse C2, respectively and will enable driving gate D1, thus e bistable unit A6 is triggered through gates 12 and 13, and completing the circuit from the power supply through R33 e voltage on A6 goes from 1 to 0, thus disabling gate 10 and potentiometer R1. R1 can now be set so that the desired d preventing the enablement of any of the driving gates. (E 35 value of voltage, 20 db. from the reference, will appear at the e 64th pulse the bistable unit A6 is again triggered and A6 output 9. in a similar manner the counts 4, 7, l0, l3, l6, 19,

turns to the 1" state, thus returning the counter to its 22, 25, 28, and 3] can be placed into the counter and the coriginal zero count state and removing the inhibit command responding potentiometers adjusted. The potentiometers corm gate 10. Thus, a simulated scan occurs every 64 pulses. responding to the unused pulses are set so that the maximum The invention may be modified by increasing or decreasing resistance appears between the gate connection and the wiper a number of states in the counter. Corresponding changes arm of the potentiometer so that no target echo pulses are ap- )Uid also be reflected in the decoder and the load potenplied to the OR gate from them. The output of the scan imeters. Multiple range and pulse widths of targets can be generator at 9 is shown in FIG. 3.

nulated by the addition of selectable circuitry, and the pulse 1 claim:

:es may be selected to generate scans other than those possi- 1. An antenna scan pattern generator for producing a simuwith the present implementation. Other types of logic elelated radar antenna pattern comprising:

:nts may also be used in the design of the digital scan pattern a. a source of an input pulse train;

nerator. All of these modifications can be made without deb. a plurality of bistable circuits interconnected to form a rting from the principles of the present embodied invention. counting circuit whose output state changes in response The scan pattern generator is also provided with means for to each pulse of said input pulse train thereby producing a librating the unit to generate a desired antenna pattern and predetermined output response;

:ans for visually observing the state of the counter. Switch 0. means for delaying said pulse train fed simultaneously is connected to the reset input of each bistable unit, and with said counting circuit by said input pulse train;

ien switch S8 is connected to ground, all the bistable units d. a first series of NAND gates selectively responsive to the reset to the 0 state. Switches S1 through S6 connect the output of said delaying means and a portion of said countat" input to ground and thus place a l into the coring circuit outputs;

:ponding bistable unit. Switch S7, when in the calibrate e. a second series of NAND gates selectively responsive to sition, disables gate 7, thus preventing the pulses from the the remaining outputs of said counting circuit;

lse generator 1 from being fed into the counter; then the f. inverting means individually connected to each of said itches S1 through S6 can be used to place any desired second series of NAND gates;

mber into the counter, and the output potentiometer corg. a third series of NAND gates selectively responsive to the .ponding to the number placed into the counter can be set outputs of said inverting means;

give the desired value of output voltage. In this manner all h. a variable resistor connected to each output of said third potentiometers R1 through R32 can be set to simulate a series of NAND gates and to avoltage source; and

en antenna pattern. After the potentiometers are set, the i. an OR gate connected to the wiper arm of each of said itch S7 is placed back in the operate position, and the variable resistors for collectively passing the output from in pattern generator will simulate the desired antenna patsaid variable resistor wiper arm to the output of said OR n. gate.

-amps Ll through L6 are connected to outputs Al through 2. The device of claim 1 further comprising means for inhibiting the output of said first series of NAND gates so that the output of the scan pattern generator may be blanked for a preselected period.

3. The device of claim ll further comprising switch means respectively of the bistable units so that a visual indication he state of the counter is provided.

\s an example of the operation of the scan pattern generathe process of generating the scan pattern resulting from antenna whose sensitivity pattern is that shown in FIG. 2 for presetting the state of said counting circuit for calibration purposes and visual means for indicating the state of said 0. said second series of NAND gates comprises eight NAND Counting cifclmgates each having three inputs, said inputs being selec- The device of claim 1 further comprising means to tively connected to the outputs of three of said bistable trol the width of the pulses from the output of said delaying multivibramrs f the counting i means- 5 d. said inverting means comprises a NAND gate; and

The devlce P whlcb e. said third series of NAND gates comprises 32 NAND a. said counting circuit comprises six serially connected gates each having two inputs, the first one of said inputs bistable multivibrators;

b. said first series of NAND gates comprises four NAND gates each having three inputs, one of said inputs selecl0 tively connected to said delay means and the remaining two inputs selectively connected to two of said bistable multivibrators of said counting circuit;

selectively connected to outputs of said first series of NAND gates and the second one of said inputs selectively connected to outputs of said second series of NAND gates. 

1. An antenna scan pattern generator for producing a simulated radar antenna pattern comprising: a. a source of an input pulse train; b. a plurality of bistable circuits intercOnnected to form a counting circuit whose output state changes in response to each pulse of said input pulse train thereby producing a predetermined output response; c. means for delaying said pulse train fed simultaneously with said counting circuit by said input pulse train; d. a first series of NAND gates selectively responsive to the output of said delaying means and a portion of said counting circuit outputs; e. a second series of NAND gates selectively responsive to the remaining outputs of said counting circuit; f. inverting means individually connected to each of said second series of NAND gates; g. a third series of NAND gates selectively responsive to the outputs of said inverting means; h. a variable resistor connected to each output of said third series of NAND gates and to a voltage source; and i. an OR gate connected to the wiper arm of each of said variable resistors for collectively passing the output from said variable resistor wiper arm to the output of said OR gate.
 2. The device of claim 1 further comprising means for inhibiting the output of said first series of NAND gates so that the output of the scan pattern generator may be blanked for a preselected period.
 3. The device of claim 1 further comprising switch means for presetting the state of said counting circuit for calibration purposes and visual means for indicating the state of said counting circuit.
 4. The device of claim 1 further comprising means to control the width of the pulses from the output of said delaying means.
 5. The device of claim 1 in which a. said counting circuit comprises six serially connected bistable multivibrators; b. said first series of NAND gates comprises four NAND gates each having three inputs, one of said inputs selectively connected to said delay means and the remaining two inputs selectively connected to two of said bistable multivibrators of said counting circuit; c. said second series of NAND gates comprises eight NAND gates each having three inputs, said inputs being selectively connected to the outputs of three of said bistable multivibrators of the counting unit; d. said inverting means comprises a NAND gate; and e. said third series of NAND gates comprises 32 NAND gates each having two inputs, the first one of said inputs selectively connected to outputs of said first series of NAND gates and the second one of said inputs selectively connected to outputs of said second series of NAND gates. 